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ltc3810-5 1 38105fd 60v current mode synchronous switching regulator controller the ltc ? 3810-5 is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 60v, making it ideal for telecom and automo - tive applications. the ltc3810-5 uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. a precise internal reference provides 0.5% dc accuracy. a high bandwidth (25mhz) error amplifier provides very fast line and load transient response. large 1 gate drivers allow the ltc3810-5 to drive multiple mosfets for higher current applications. the operating frequency is selected by an external resistor and is compensated for variations in v in and can also be synchronized to an external clock for switching-noise sensitive applications. a shutdown pin allows the ltc3810-5 to be turned off, reducing the supply current to 240a. integrated bias control generates gate drive power from the input supply during start-up or when an output short- circuit occurs, with the addition of a small external sot23 mosfet. when in regulation, power is derived from the output for higher efficiency. n 48v telecom and base station power supplies n networking equipment, servers n automotive and industrial control systems n high voltage operation: up to 60v n large 1 gate drivers n no current sense resistor required n dual n-channel mosfet synchronous drive n extremely fast transient response n 0.5% 0.8v voltage reference n programmable output voltage t racking/soft-start n generates 5.5v driver supply from input supply n synchronizable to external clock n selectable pulse skip mode operation n power good output voltage monitor n adjustable on-time/frequency: t on(min) < 100ns n adjustable cycle-by-cycle current limit n programmable undervoltage lockout n output overvoltage protection n 5mm 5mm qfn package high efficiency high voltage step-down converter efficiency vs load current typical a pplica t ion fea t ures a pplica t ions descrip t ion l , lt, ltc, ltm, linear technology, the linear logo and no r sense are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611. pgood mode/sync v rng i th v fb sgnd ss/track i on 1000pf 47pf 5pf v in 13v to 60v 22f v out 12v/6a zxmn10a07f 200k ltc3810-5 extv cc tg sw sense ? bg bgrtn sense + drv cc intv cc ndrv boost 38105 ta01 0.1f 274k 100k si7450dp si7450dp 1 f mbr1100 14k 1k 270f 10h shdn + + load current (a) 0 85 efficiency (%) 90 95 100 1 2 3 4 38105 ta01b 5 6 v in = 24v v in = 42v
ltc3810-5 2 38105fd supply voltages intv cc , drv cc ...................................... C0 .3v to 14v (drv cc C bgrtn), (boost C sw) ........ C0 .3v to 14v boost (continuous) .............................. C 0.3v to 85v boost (400ms) .................................. C 0.3v to 95v bgrtn ........................................................ C 5v to 0v extv cc .................................................. C0 .3v to 15v (extv cc C intv cc ) .................................. C12 v to 12v (ndrv C intv cc ) voltage .......................... C 0.3v to 10v sw, sense + voltage (continuous) ................. C 1v to 70v sw, sense + voltage (400ms) ........................ C 1v to 80v i on voltage (continuous) ............................ C 0.3v to 70v i on voltage (400ms) ................................... C 0.3v to 80v ss/track voltage ....................................... C 0.3v to 5v pgood voltage ............................................ C 0.3v to 7v v rng , v on , mode/sync, shdn , uvin voltages ............................................ C 0.3v to 14v pll/lpf, fb voltages ................................ C 0.3v to 2.7v tg, bg, intv cc , extv cc rms currents ................ 5 0ma operating junction temperature range (notes 2, 3, 7) ltc3810e-5 ....................................... C 40c to 125c ltc3810i-5 ........................................ C 40c to 125 c ltc 3810h-5 ....................................... C4 0c to 150c storage temperature range .................. C 65c to 125c (note 1) p in c on f igura t ion a bsolu t e maxi m u m r a t ings 32 33 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1nc v on v rng pgood mode/sync i th v fb pll/lpf sense + nc nc nc sense ? bgrtn bg drv cc nc i on nc nc nc boost tg sw ss/track nc nc shdn uvin ndrv extv cc intv cc t jmax = 125c, v ja = 34c/w exposed pad (pin 33) is sgnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3810euh-5#pbf ltc3810euh-5#trpbf 38105 32-lead (5mm w 5mm) plastic qfn C40c to 125c ltc3810iuh-5#pbf ltc3810iuh-5#trpbf 38105 32-lead (5mm w 5mm) plastic qfn C40c to 125c lead based finish tape and reel part marking package description temperature range ltc3810euh-5 ltc3810euh-5#tr 38105 32-lead (5mm w 5mm) plastic qfn C40c to 125c ltc3810iuh-5 ltc3810iuh-5#tr 38105 32-lead (5mm w 5mm) plastic qfn C40c to 125c ltc3810huh-5 ltc3810huh-5#tr 38105 32-lead (5mm w 5mm) plastic qfn C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc3810-5 3 38105fd symbol parameter conditions min typ max units main control loop intv cc intv cc supply voltage l 4.35 14 v i q intv cc supply current intv cc shutdown current shdn > 1.5v (notes 4, 5) shdn = 0v 3 240 6 600 ma a i boost boost supply current shdn > 1.5v (note 5) shdn = 0v 270 0 400 5 a a v fb feedback voltage (note 4) 0c to 85c C40c to 85c C40c to 125c (i-grade) C40c to 150c (h-grade) l l l l 0.796 0.794 0.792 0.792 0.792 0.800 0.800 0.800 0.800 0.800 0.804 0.806 0.806 0.808 0.812 v v v v v dv fb,line feedback voltage line regulation 5v < intv cc < 14v (note 4) l 0.002 0.02 %/v v sense(max) maximum current sense threshold v rng = 2v, v fb = 0.76v v rng = 0v, v fb = 0.76v v rng = intv cc , v fb = 0.76v 256 70 170 320 95 215 384 120 260 mv mv mv v sense(min) minimum current sense threshold v rng = 2v, v fb = 0.84v v rng = 0v, v fb = 0.84v v rng = intv cc , v fb = 0.84v C300 C85 C200 mv mv mv i vfb feedback current v fb = 0.8v 20 150 na a vol (ea) error amplifier dc open loop gain 65 100 db f u error amp unity-gain crossover frequency (note 6) 25 mhz v mode/sync mode/sync threshold v mode/sync rising 0.75 0.8 0.85 v i mode/sync mode/sync current mode/sync = 5v 0 1 a v shdn shutdown threshold 1.2 1.5 2 v i shdn shdn pin input current 0 1 a v uvin uvin undervoltage lockout uvin rising uvin falling hysteresis l l 0.86 0.78 0.07 0.89 0.80 0.10 0.92 0.82 0.12 v v v v vccuv intv cc undervoltage lockout linear regulator mode external supply mode trickle-charge mode intv cc rising, i ndrv = 100a intv cc rising, ndrv = intv cc = extv cc intv cc rising, ndrv = intv cc , extv cc = 0 intv cc falling l l l 4.05 4.05 8.70 4.2 4.2 9 3.7 4.35 4.35 9.30 v v v v oscillator and phase-locked loop t on on-time i on = 100a i on = 300a 1.55 515 1.85 605 2.15 695 s ns t on(min) minimum on-time i on = 2000a 100 ns t off(min) minimum off-time 250 350 ns t on(pll) t on modulation range by pll down modulation up modulation i on = 100a, v pll/lpf = 0.6v i on = 100a, v pll/lpf = 1.8v 2.2 0.6 3.6 1.2 5 1.8 s s i pll/lpf phase detector output current sinking capability sourcing capability f pllin < f sw f pllin > f sw 15 C25 a a driver i bg,peak bg driver peak source current v bg = 0v 0.7 1 a r bg,sink bg driver pull-down r ds(on) 1 1.5 ? i tg,peak tg driver peak source current v tg C v sw = 0 0.7 1 a r tg,sink tg driver pull-down r ds(on) 1 1.5 ? the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2), intv cc = drv cc = v boost = v on = v rng = shdn = uv in = v extvcc = v ndrv = 5v, v mode/sync = v sense + = v sense C = v bgrtn = v sw = 0v, unless otherwise specified. e lec t rical c harac t eris t ics
ltc3810-5 4 38105fd note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3810-5 is tested under pulsed load conditions such that t j t a . the ltc3810e-5 is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3810i-5 is guaranteed to meet performance specifications over the full C40c to 125c operating junction temperature range. the ltc3810h-5 is guaranteed to meet performance specifications over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note 3: t j is calculated from the ambient temperature t a and power symbol parameter conditions min typ max units pgood output dv fbov pgood upper threshold pgood lower threshold v fb rising v fb falling 7.5 C7.5 10 C10 12.5 C12.5 % % dv fb,hyst pgood hysterisis v fb returning 1.5 3 % v pgood pgood low voltage i pgood = 5ma 0.3 0.6 v i pgood pgood leakage current v pgood = 5v 0 2 a pg delay pgood delay v fb falling 120 s tracking i ss/track ss/track source current v ss/track > 0.5v 0.7 1.4 2.5 a v fb,track feedback voltage at tracking v track = 0v, i th = 1.2v (note 4) v track = 0.5v, i th = 1.2v (note 4) 0.48 C0.018 0.5 0.52 v v v cc regulators v extvcc extv cc switchover voltage extv cc rising extv cc hysterisis l 4.45 0.1 4.7 0.25 0.4 v v v intvcc,1 intv cc voltage from extv cc 6v < v extvcc < 15v 5.2 5.5 5.8 v dv extvcc,1 v extvcc - v intvcc at dropout i cc = 20ma, v extvcc = 5v 75 150 mv dv loadreg,1 intv cc load regulation from extv cc i cc = 0ma to 20ma, v extvcc = 10v 0.01 % v intvcc,2 intv cc voltage from ndrv regulator linear regulator in operation 5.2 5.5 5.8 v dv loadreg,2 intv cc load regulation from ndrv i cc = 0ma to 20ma, v extvcc = 0 0.01 % i ndrv current into ndrv pin v ndrv C v intvcc = 3v 20 40 60 a i ndrvto linear regulator timeout enable threshold 210 270 350 a v ccsr maximum supply voltage trickle charger shunt regulator 15 v i ccsr maximum current into ndrv/intv cc trickle charger shunt regulator, intv cc 16.7v (note 8) 10 ma the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2), intv cc = drv cc = v boost = v on = v rng = shdn = uv in = v extvcc = v ndrv = 5v, v mode/sync = v sense + = v sense C = v bgrtn = v sw = 0v, unless otherwise specified. dissipation p d according to the following formula: ltc3810-5: t j = t a + (p d ? 34c/w) note 4: the ltc3810-5 is tested in a feedback loop that servos v fb to the reference voltage with the i th pin forced to a voltage between 1v and 2v. note 5: the dynamic input supply current is higher due to the power mosfet gate charging being delivered at the switching frequency (q g ? f osc ). note 6: guaranteed by design. not subject to test. note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 8: i cc is the sum of current into ndrv and intv cc . similar parts comparison parameter ltc3810 ltc3810-5 ltc3812-5 maximum v in 100v 60v 60v mosfet gate drive 6.35v to 14v 4.5v to 14v 4.5v to 14v intv cc uv + 6.2v 4.2v 4.2v intv cc uv C 6v 4v 4v elec t rical charac t eris t ics
ltc3810-5 5 38105fd load transient response start-up short-circuit/ fault timeout operation short-circuit/ foldback operation tracking pulse skip mode operation efficiency vs input voltage efficiency vs load current frequency vs input voltage typical p er f or m ance c harac t eris t ics 50s/div v out 100mv/div i out 5a/div 38105 g01 v in = 48v 0a to 5a loadstep front page circuit 500s/div intv cc 5v/div v out 5v/div v in 50v/div i l 5a/div 38105 g02 v in = 48v i load = 1a mode/sync = 0v front page circuit intv cc 10ms/div v out 10v/div ss/track 4v/div i l 5a/div 38105 g03 v in = 48v r short = 0.1 front page circuit 200s/div v out 5v/div v fb 0.5v/div i l 5a/div 38105 g04 v in = 48v front page circuit 500s/div 38105 g05 v out 5v/div ss/track 0.5v/div v fb 0.5v/div i l 5a/div v in = 48v i load = 1a mode/sync = 0v front page circuit ss/track v fb v out 100mv/div i th 0.5v/div 20s/div 38105 g06 i l 2a/div v in = 48v i out = 100ma mode/sync = intv cc front page circuit input voltage (v) 10 20 70 efficiency (%) 90 100 30 50 60 38105 g07 80 40 70 80 i out = 5a i out = 0.5a v out = 12v si7852 mosfets f = 250khz load current (a) 0 70 efficiency (%) 75 80 85 90 100 1 2 3 4 38105 g08 5 76 95 v out = 5v si7850 mosfets mode/sync = intv cc f = 250khz v in = 12v v in = 36v v in = 60v input voltage (v) 10 20 230 frequency (khz) 250 280 30 50 60 38105 g09 240 270 260 40 70 80 i out = 0a i out = 5a mode/sync = 0v front page circuit
ltc3810-5 6 38105fd frequency vs load current current sense threshold vs i th voltage on-time vs i on current on-time vs v on voltage on-time vs temperature current limit foldback maximum current sense threshold vs v rng voltage maximum current sense threshold vs temperature reference voltage vs temperature typical p er f or m ance c harac t eris t ics load current (a) 0 250 300 350 4 38105 g10 200 150 1 2 3 5 100 50 0 frequency (khz) forced continuous pulse skip i th voltage (v) 0 current sense threshold (mv) ?100 0 100 1.5 2.5 38105 g11 ?200 ?300 ?400 0.5 1.0 2.0 200 300 400 3.0 v rng = 2v 1.4v 1v 0.7v 0.5v i on current (a) 10 10 on-time (ns) 100 1000 10000 100 1000 10000 38105 g12 v on = intv cc v on voltage (v) 0 400 500 700 1.5 2.5 38105 g13 300 200 0.5 1 2 3 100 0 600 on-time (ns) i on = 300a temperature (c) ?50 on-time (ns) 640 660 680 25 75 38105 g14 620 600 ?25 0 50 100 150125 580 560 i on = 300a v fb (v) 0 maximum current sense threshold (mv) 100 150 0.8 38105 g15 50 0 0.2 0.4 0.6 250 200 v rng = intv cc v rng voltage (v) 0.5 maximum current sense threshold (mv) 200 38105 g16 100 0 1 1.5 300 400 2 ?50 25 75 ?25 0 50 100 150125 temperature ( c) 180 maximum current sense threshold (mv) 200 230 38105 g17 190 220 210 v rng = intv cc ?50 25 75 ?25 0 50 100 150125 temperature (c) reference voltage (v) 0.801 0.802 0.803 38105 g18 0.800 0.799 0.798 0.797
ltc3810-5 7 38105fd driver peak source current vs temperature driver pull-down r ds(on) vs temperature driver peak source current vs supply voltage driver pull-down r ds(on) vs supply voltage extv cc ldo resistance at dropout vs temperature intv cc current vs temperature intv cc shutdown current vs temperature intv cc current vs intv cc voltage typical p er f or m ance c harac t eris t ics ?50 25 75 ?25 0 50 100 150125 temperature (c) 0.5 peak source current (a) 1.0 1.5 38105 g19 v boost = v intvcc = 5v ?50 25 75 ?25 0 50 100 150125 temperature (c) r ds(on) (?) 1.25 1.50 1.75 38105 g20 1.00 0.75 0.50 0.25 v boost = v intvcc = 5v drv cc /boost voltage (v) 4 5 7 9 11 13 peak source current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 6 8 10 12 38105 g21 14 drv cc /boost voltage (v) 4 r ds(on) () 0.6 0.8 0.9 1.0 1.1 6 8 9 1413 38105 g22 0.7 5 7 10 11 12 ?50 25 75 ?25 0 50 100 150125 temperature (c) 4 5 7 38105 g23 3 2 1 0 6 resistance () ?50 25 75 ?25 0 50 100 150125 temperature (c) 1 intv cc current (ma) 2 5 4 3 ?50 25 75 ?25 0 50 100 150125 temperature (c) intv cc current (a) 38105 g25 200 100 0 400 300 intv cc = 5v intv cc voltage (v) 0 2.0 2.5 3.5 6 10 38105 g26 1.5 1.0 2 4 8 12 14 0.5 0 3.0 intv cc current (ma)
ltc3810-5 8 38105fd intv cc shutdown current vs intv cc voltage ss/track pull-up current vs temperature i th voltage vs load current shutdown threshold vs temperature typical p er f or m ance c harac t eris t ics intv cc voltage (v) 0 200 250 300 6 10 38105 g27 150 100 2 4 8 12 14 50 0 intv cc current (a) ?50 25 75 ?25 0 50 100 150125 temperature (c) ss/track current (a) 2 3 38105 g28 1 0 load current (a) 0 2.0 3.0 2.5 3 5 38105 g29 1.5 1.0 1 2 4 6 7 0.5 0 i th voltage (v) v rng = 1v front page circuit ?50 25 75 ?25 0 50 100 150125 temperature (c) shutdown threshold (v) 2.0 38105 g30 1.4 1.0 0.8 0.6 2.2 1.8 1.6 1.2
ltc3810-5 9 38105fd p in func t ions v on (pin 2): on-time voltage input. voltage trip point for the on-time comparator. tying this pin to the output voltage or to an external resistive divider from the output makes the on-time proportional to v out . the comparator defaults to 0.7v when the pin is grounded and defaults to 2.4v when the pin is connected to intv cc . tie this pin to intv cc in high v out applications to use a lower r on value. v rng (pin 3): sense voltage limit set. the voltage at this pin sets the nominal sense voltage at maximum output current and can be set from 0.5v to 2v by a resistive di- vider from intv cc . the nominal sense voltage defaults to 95mv when this pin is tied to ground, and 215mv when tied to intv cc . pgood (pin 4): power good output. open-drain logic output that is pulled to ground when the output voltage is not between 10% of the regulation point. the output voltage must be out of regulation for at least 120s before the power good output is pulled to ground. mode/sync (pin 5): pulse skip mode enable/sync pin. this multifunction pin provides pulse skip mode enable/ disable control and an external clock input to the phase detector. pulling this pin below 0.8v or to an external logic-level synchronization signal disables pulse skip mode operation and forces continuous operation. pulling this pin above 0.8v enables pulse skip mode operation. for a clock input, the phase-locked loop will force the rising top gate signal to be synchronized with the rising edge of the clock signal.this pin can also be connected to a feedback resistor divider from a secondary winding on the inductor to regulate a second output voltage. i th (pin 6): error amplifier compensation point and cur - rent control threshold. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.6v with 1.2v corresponding to zero sense voltage (zero current). v fb (pin 7): feedback input. connect v fb through a resistor divider network to v out to set the output voltage. pll/lpf (pin 8): the phase-locked loops lowpass filter is tied to this pin. the voltage at this pin defaults to 1.2v when the ic is not synchronized with an external clock at the mode/sync pin. ss/track (pin 9): soft-start/tracking input. for soft-start, a capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 0.6s/f). for coincident or ratiometric tracking, connect this pin to a resistive divider between the voltage to be tracked and ground. shdn (pin 12): shutdown pin. pulling this pin below 1.5v will shut down the ltc3810-5, turn off both of the external mosfet switches and reduce the quiescent sup- ply current to 240a. uvin (pin 13): uvlo input. this pin is input to the internal uvlo and is compared to an internal 0.8v reference. an external resistor divider is connected to this pin and the input supply to program the undervoltage lockout voltage. when uvin is less than 0.8v, the ltc3810-5 is shut down. ndrv (pin 14): drive output for external pass device of the linear regulator for intv cc . connect to the gate of an external nmos pass device and a pull-up resistor to the input voltage v in . extv cc (pin 15): external driver supply voltage. when this voltage exceeds 4.7v, an internal switch connects this pin to intv cc through an ldo and turns off the exter nal mosfet connected to ndrv, so that controller and gate drive are drawn from extv cc . intv cc (pin 16): main supply pin. all internal circuits ex - cept the output drivers are powered from this pin. intv cc should be bypassed to ground (pin 10) with at least a 0.1f capacitor in close proximity to the ltc3810-5. drv cc (pin 17): driver supply pin. drv cc supplies power to the bg output driver. this pin is normally connected to intv cc . drv cc should be bypassed to bgrtn (pin 20) with a low esr (x5r or better) 1f-10f capacitor in close proximity to the ltc3810-5.
ltc3810-5 10 38105fd pin f unc t ions bg (pin 18): bottom gate drive. the bg pin drives the gate of the bottom n-channel synchronous switch mosfet. this pin swings from bgrtn to drv cc . bgrtn (pin 19): bottom gate return. this pin connects to the source of the pulldown mosfet in the bg driver and is normally connected to ground. connecting a negative supply to this pin allows the synchronous mosfet s gate to be pulled below ground to help prevent false turn-on during high dv /dt transitions on the sw node. see the applications information section for more details. sense + , sense C (pin 24, pin 20): current sense com- parator input. the (+) input to the current comparator is normally connected to sw unless using a sense resistor. the (C) input is used to accurately kelvin sense the bottom side of the sense resistor or mosfet. sw (pin 25): switch node connection to inductor and bootstrap capacitor. the voltage swing at this pin is C0.7v (a schottky diode (external) voltage drop) to v in . tg (pin 26): top gate drive. the tg pin drives the gate of the top n-channel synchronous switch mosfet. the tg driver draws power from the boost pin and returns to the sw pin, providing true floating drive to the top mosfet. boost (pin 27): top gate driver supply. the boost pin supplies power to the floating tg driver. boost should be bypassed to sw with a low esr (x5r or better) 0.1f capacitor. an additional fast recovery schottky diode from drv cc to the boost pin will create a complete floating charge-pumped supply at boost. i on (pin 31): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. sgnd (exposed pad pin 33): signal ground. all small- signal components should connect to this ground and eventually connect to pgnd at one point.
ltc3810-5 11 38105fd func t ional diagra m ? + ? + 1.4v fault 0.7v fb v rng 3 ? + ? + + ? + v von i ion t on = (76pf) r s q 20k i cmp i rev shdn switch logic bg on fcnt ov 1.5v ea 0.8v 12 38105 fd sgnd r fb1 r fb2 12 run shdn 18 bgrtn 19 pgood v fb drv cc 17 sense + 24 sw 25 tg boost c b 26 27 extv cc 15 intv cc ndrv 16 14 ? + ? + uv 0.72v ov 0.88v c vcc v out m2 m1 m3 l1 c out c in + ss/track d b 4 + + v in v in sense ? 20 ? + overtemp sense foldback 0.8v ref 5v reg intv cc i th ? 5 8 i on 31 v in v in 2 v on pll/lpf mode/sync uvin r on 0.8v r uv1 r uv2 ? + f timeout logic intv cc mode logic n drv extv cc intv cc pll-sync ? + v in uv 13 ? + intv cc uv drv off 100na 1.4a 270a ? + ? + off on 5.5v 4.7v 4.2v 9v 5.5v shdn 2.6v 4v i th c c2 6 r c c c1 9 7
ltc3810-5 12 38105fd main control loop the ltc3810-5 is a current mode controller for dc/ dc step-down converters. in normal operation, the top mosfet is turned on for a fixed interval determined by a one-shot timer (ost). when the top mosfet is turned off, the bottom mosfet is turned on until the current comparator i cmp trips, restarting the one-shot timer and initiating the next cycle. inductor current is determined by sensing the voltage between the sense C and sense + pins using a sense resistor or the bottom mosfet on- resistance. the voltage on the i th pin sets the comparator threshold corresponding to the inductor valley current. the fast 25mhz error amplifier ea adjusts this voltage by comparing the feedback signal v fb to the internal 0.8v reference voltage. if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to maintain regulation. the one-shot timer generates an on time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor r on . for applications with stringent constant frequency re- quirements, the ltc3810-5 can be synchronized with an external clock. by programming the nominal frequency the same as the external clock frequency, the ltc3810-5 behaves as a constant frequency part against the load and supply variations. pulling the shdn pin low forces the controller into its shutdown state, turning off both m1 and m2. forcing a voltage above 1.5v will turn on the device. pulse skip mode the ltc3810-5 can operate in one of two modes selectable with the mode/sync pinpulse skip mode or forced con - tinuous mode (see figure 1). pulse skip mode is selected when increased efficiency at light loads is desired (see figure 2). in this mode, the bottom mosfet is turned off when inductor current reverses to minimize efficiency loss due to reverse current flow and gate charge switching. at low load currents, i th will drop below the zero current level (1.2v) shutting off both switches. both switches will remain off with the output capacitor supplying the load current until the i th voltage rises above the zero current level to initiate another cycle. in this mode, frequency is proportional to load current at light loads. pulse skip mode operation is disabled by comparator f when the mode/sync pin is brought below 0.8v, forcing continuous synchronous operation. forced continuous mode is less efficient due to resistive losses, but has the advantage of better transient response at low currents, approximately constant frequency operation, and the ability to maintain regulation when sinking current. figure 1. comparison of inductor current waveforms for pulse skip mode and forced continuous operation o pera t ion figure 2. efficiency in pulse skip/ forced continuous modes decreasing load current 38105 f01 pulse skip mode 0a 0a 0a 0a 0a 0a forced continuous load (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 38105 f02 30 20 10 0 90 100 v in = 12v v in = 42v pulse skip forced continuous
ltc3810-5 13 38105fd fault monitoring/protection constant on-time current mode architecture provides ac - curate cycle-by-cycle current limit protectiona feature that is very important for protecting the high voltage power supply from output short circuits. the cycle-by-cycle cur - rent monitor guarantees that the inductor current will never exceed the value programmed on the v rng pin. foldback current limiting provides further protection if the output is shorted to ground. as v fb drops, the buffered current threshold voltage i thb is pulled down and clamped to 1v. this reduces the inductor valley current level to one-sixth of its maximum value as v fb approaches 0v. foldback current limiting is disabled at start-up. overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback voltage exits a 10% window around the regulation point after the internal 120s power bad mask timer expires. furthermore, in an overvoltage condition, m1 is turned off and m2 is turned on immediately and held on until the overvoltage condition clears. the ltc3810-5 provides two undervoltage lockout com - paratorsone for the intv cc /drv cc supply and one for the input supply v in . the intv cc uv threshold is 4.2v to guarantee that the mosfets have sufficient gate drive voltage before turning on. the v in uv threshold (uvin pin) is 0.8v with 10% hysteresis which allows programming the v in threshold with the appropriate resistor divider connected to v in . if either comparator inputs are under the uv threshold, the ltc3810-5 is shut down and the drivers are turned off. strong gate drivers the ltc3810-5 contains very low impedance drivers ca - pable of supplying amps of current to slew large mosfet gates quickly. this minimizes transition losses and allows paralleling mosfets for higher current applications. a 60v floating high side driver drives the top side mosfet and a low side driver drives the bottom side mosfet (see figure 3). the bottom side driver is supplied directly from the drv cc pin. the top mosfet drivers are biased from floating bootstrap capacitor, c b , which normally is recharged during each off cycle through an external diode from drv cc when the top mosfet turns off. in pulse skip mode operation, where it is possible that the bottom mosfet will be off for an extended period of time, an internal timeout guarantees that the bottom mosfet is turned on at least once every 25s for one on-time period to refresh the bootstrap capacitor. the bottom driver has an additional feature that helps minimize the possibility of external mosfet shoot-through. when the top mosfet turns on, the switch node dv/dt pulls up the bottom mosfets internal gate through the miller capacitance, even when the bottom driver is holding the gate terminal at ground. if the gate is pulled up high enough, shoot-through between the top side and bottom side mosfets can occur. to prevent this from occurring, the bottom driver return is brought out as a separate pin (bgrtn) so that a negative supply can be used to reduce the effect of the miller pull-up. for example, if a C2v sup- ply is used on bgrtn, the switch node dv/dt could pull the gate up 2v before the v gs of the bottom mosfet has more than 0v across it. figure 3. floating tg driver supply and negative bg return opera t ion boost tg sw bg bgrtn drv cc drv cc ltc3810-5 m1 m2 + + v in c in v out c out d b c b l 38105 f03 0v to ?5v ic/driver supply power the ltc3810-5s internal control circuitry and top and bottom mosfet drivers operate from a supply voltage (intv cc , drv cc pins) in the range of 4.5v to 14v. the ltc3810-5 has two integrated linear regulator controllers to easily generate this ic/driver supply from either the high voltage input or from the output voltage. for best efficiency the supply is derived from the input voltage during start-up and then derived from the lower voltage output as soon as the output is higher than 4.7v. alternatively, the supply can be derived from the input continuously if the output is
ltc3810-5 14 38105fd <4.7v or an external supply in the appropriate range can be used. the ltc3810-5 will automatically detect which mode is being used and operate properly. the four possible operating modes for generating this supply are summarized as follows (see figure 4): 1. ltc3810-5 generates a 5.5v start-up supply from a small external sot23 n-channel mosfet acting as linear regulator with drain connected to v in and gate controlled by the ltc3810-5s internal linear regulator controller through the ndrv pin. as soon as the output voltage reaches 4.7v, the 5.5v ic/driver supply is derived from the output through an internal low-dropout regulator to optimize efficiency. if the output is lost due to a short, the ltc3810-5 goes through repeated low duty cycle soft-start cycles (with the drivers shut off in between) to attempt to bring up the output without burning up the sot23 mosfet. this scheme eliminates the long start-up times associated with a conventional trickle charger by using an external mosfet to quickly charge the ic/driver supply capacitors (c intvcc , c drvcc ). 2 . similar to (1) except that the external mosfet is used for continuous ic/driver power instead of just for start-up. the mosfet is sized for proper dissipation and the driver shutdown/restart for v out < 4.7v is disabled. this scheme is less efficient but may be necessary if v out < 4.7v and a boost network is not desired. 3. trickle charge mode provides an even simpler approach by eliminating the external mosfet. the ic/driver sup - ply capacitors are charged through a single high-valued resistor connected to the input supply. when the intv cc voltage reaches the turn-on threshold of 9v (automati - cally raised from 4.7v to provide extra headroom for start-up), the drivers turn on and begin charging up the output capacitor. when the output reaches 4.7v, ic/driver power is derived from the output. in trickle-charge mode, the supply capacitors must have sufficient capacitance such that they are not discharged below the 4v intv cc uv threshold before the output is high enough to take over or else the power supply will not start. 4. low voltage supply available. the simplest approach is if a low voltage supply (between 4.5v and 14v) is avail - able and connected directly to the ic/driver supply pins. figure 4. operating modes for ic/driver supply ndrv extv cc intv cc v out (> 4.7v) v in i < 270a v out + ? mode 1: mosfet for start-up only mode 2: mosfet for continuous use mode 3: trickle charge mode mode 4: external supply 5.5v 4.5v to 14v 38105 f04 ndrv extv cc intv cc ndrv extv cc intv cc ndrv extv cc intv cc v in i > 270a 5.5v + + + v in 5.5v + ltc3810-5 ltc3810-5 ltc3810-5 ltc3810-5 o pera t ion
ltc3810-5 15 38105fd the basic ltc3810-5 application circuit is shown on the first page of this data sheet. external component selection is primarily determined by the maximum input voltage and load current and begins with the selection of the sense resistance and power mosfet switches. the ltc3810-5 uses either a sense resistor or the on-resistance of the synchronous power mosfet for determining the inductor current. the desired amount of ripple current and operating frequency largely determines the inductor value. next, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specification. finally, loop compensation components are selected to meet the required transient/phase margin specifications. maximum sense voltage and v rng pin inductor current is determined by measuring the volt- age across a sense resistance that appears between the sense C and sense + pins. the maximum sense voltage is set by the voltage applied to the v rng pin and is equal to approximately: v sense(max) = 0.173v rng C 0.026 the current mode control loop will not allow the inductor current valleys to exceed v sense(max) /r sense . in prac- tice, one should allow some margin for variations in the ltc3810-5 and external component values and a good guide for selecting the sense resistance is: r sense = v sense(max) 1.3 ? i out(max) an external resistive divider from intv cc can be used to set the voltage of the v rng pin between 0.5v and 2v resulting in nominal sense voltages of 60mv to 320mv. additionally, the v rng pin can be tied to sgnd or intv cc in which case the nominal sense voltage defaults to 95mv or 215mv, respectively. connecting the sense + and sense C pins the ltc3810-5 can be used with or without a sense re - sistor. when using a sense resistor, place it between the source of the bottom mosfet, m2 and pgnd. connect the sense + and sense C pins to the top and bottom of the sense resistor. using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. alternatively, one can eliminate the sense resistor and use the bottom mosfet as the current sense element by simply connecting the sense + pin to the lower mosfet drain and sense C pin to the mosfet source. this improves efficiency, but one must carefully choose the mosfet on-resistance, as discussed below. power mosfet selection the ltc3810-5 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage bv dss , threshold voltage v (gs)th , on-resistance r ds(on) , input capacitance and maximum current i ds(max) . when the bottom mosfet is used as the current sense element, particular attention must be paid to its on- resistance. mosfet on-resistance is typically specified with a maximum value r ds(on)(max) at 25c. in this case, additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r ds(on)(max) = r sense t the t term is a normalization factor (unity at 25c) accounting for the significant variation in on-resistance with temperature (see figure 5) and typically varies from 0.4%/ c to 1.0%/ c depending on the particular mosfet used. figure 5. r ds(on) vs temperature junction temperature ( c) ?50 t normalized on-resistance 1.0 1.5 150 38105 f05 0.5 0 0 50 100 2.0 a pplica t ions i n f or m a t ion
ltc3810-5 16 38105fd the most important parameter in high voltage applications is breakdown voltage bv dss . both the top and bottom mosfets will see full input voltage plus any additional ringing on the switch node across its drain-to-source dur - ing its off-time and must be chosen with the appropriate breakdown specification. the ltc3810-5 is designed to be used with a 4.5v to 14v gate drive supply (drv cc pin) for driving logic-level mosfets (v gs(min) 4.5v). for maximum efficiency, on-resistance r ds(on) and input capacitance should be minimized. low r ds(on) minimizes conduction losses and low input capacitance minimizes transition losses. mosfet input capacitance is a combi- nation of several components but can be taken from the typical gate charge curve included on most data sheets (figure 6). the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in the power dissipation for the main and synchronous mosfets at maximum output current are given by: p top = v out v in i max ( ) 2 ( t )r ds(on) + v in 2 i max 2 (r dr )(c miller ) ? 1 v cc ? v th(il) + 1 v th(il) ? ? ? ? ? ? ? ? (f) p bot = v in ? v out v in (i max ) 2 ( t )r ds(0n) where t is the temperature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(il) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n-channel equation incudes an additional term for transition losses, which peak at the highest input voltage. for high input voltage low duty cycle applications that are typical for the ltc3810-5, transition losses are the dominate loss term and therefore using higher r ds(on) device with lower c miller usually provides the highest efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of figure 6. gate charge characteristic + ? v ds v in v gs miller effect q in a b c miller = (q b ? q a )/v ds v gs v + ? 38105 f06 applica t ions in f or m a t ion the curve is generated by forcing a constant input cur - rent into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage specified. c miller is the most important se - lection criteria for determining the transition loss term in
ltc3810-5 17 38105fd the period. since there is no transition loss term in the synchronous mosfet, optimal efficiency is obtained by minimizing r ds(on) by using larger mosfets or paral - leling multiple mosfets. multiple mosfets can be used in parallel to lower r ds(on) and meet the current and thermal requirements if desired. the ltc3810-5 contains large low impedance drivers capable of driving large gate capacitances without significantly slowing transition times. in fact, when driv- ing mosfets with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (10 or less) to reduce noise and emi caused by the fast transitions. operating frequency the choice of operating frequency is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of ltc3810-5 applications is determined implicitly by the one-shot timer that controls the on-time, t on , of the top mosfet switch. the on-time is set by the current out of the i on pin and the voltage at the v on pin according to: t on = v von i ion (76pf) tying a resistor r on from v in to the i on pin yields an on-time inversely proportional to v in . for a step-down converter, this results in approximately constant frequency operation as the input supply varies: f = v out v von ? r on (76pf) [h z ] to hold frequency constant during output voltage changes, tie the v on pin to v out or to a resistive divider from v out when v out > 2.4v. the v on pin has internal clamps that limit its input to the one-shot timer. if the pin is tied below 0.7v, the input to the one-shot is clamped at 0.7v. similarly, if the pin is tied above 2.4v, the input is clamped at 2.4v. in high v out applications, tie v on to intv cc . figures 7a and 7b show how r on relates to switching frequency for several common output voltages. changes in the load current magnitude will cause fre- quency shift. parasitic resistance in the mosfet switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. by lengthening the on-time slightly as current increases, constant frequency operation can be maintained. this is accomplished with a resistive divider from the i th pin to the v on pin and v out . the values required will depend on the parasitic resistances in the specific application. a good starting point is to feed about 25% of the voltage change at the i th pin to the v on pin as shown in figure 8. place capacitance on the v on pin to filter out the i th variations at the switching frequency. figure 7a. switching frequency vs r on (v on = 0v) figure 7b. switching frequency vs r on (v on = intv cc ) r on (k) 10 100 switching frequency (khz) 1000 100 1000 38105 f07a v out = 1.5v v out = 5v v out = 2.5v v out = 3.3v r on (k) 10 100 switching frequency (khz) 1000 100 1000 38105 f07b v out = 3.3v v out = 12v v out = 5v a pplica t ions i n f or m a t ion
ltc3810-5 18 38105fd minimum off-time and dropout operation the minimum off-time t off(min) is the smallest amount of time that the ltc3810-5 is capable of turning on the bot - tom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 250ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: v in(min) = v out t on + t off(min) t on a plot of maximum duty cycle vs frequency is shown in figure 9. inductor selection given the desired input and output voltages, the induc- tor value and operating frequency determine the ripple current: i l = v out f l ? ? ? ? ? ? 1? v out v in ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l = v out f i l(max) ? ? ? ? ? ? 1? v out v in(max) ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m ? cores. a variety of inductors designed for high current, low voltage applications are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft and toko. schottky diode d1 selection the schottky diode d1 shown in the front page schematic conducts during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diode of the bottom mosfet from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. the diode can be rated for about one-half to one-fifth of the full load current since it is on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between it c von 0.01f r von2 30k r von1 100k intv cc 5.5v 100k v on i th ltc3810-5 38105 f08 2.0 1.5 1.0 0.5 0 0 0.25 0.50 0.75 38105 f09 1.0 dropout region duty cycle (v out /v in ) switching frequency (mhz) applica t ions in f or m a t ion figure 9. maximum switching frequency vs duty cycle figure 8. correcting frequency shift with load current changes
ltc3810-5 19 38105fd and the bottom mosfet must be as small as possible, mandating that these components be placed adjacently. the diode can be omitted if the efficiency loss is tolerable. input capacitor selection in continuous mode, the drain current of the top mosfet is approximately a square wave of duty cycle v out /v in which must be supplied by the input capacitor. to prevent large input transients, a low esr input capacitor sized for the maximum rms current is given by: i cin(rms) ? i o(max) v out v in v in v out ? 1 ? ? ? ? ? ? 1/2 this formula has a maximum at v in = 2v out , where i rms = i o(max) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. because tantalum and os-con capacitors are not available in voltages above 30v, ceramics or aluminum electrolytics must be used for regulators with input supplies above 30v. ceramic capacitors have the advantage of very low esr and can handle high rms current, but ceramics with high voltage ratings (> 50v) are not available with more than a few microfarads of capacitance. furthermore, ceram- ics have high voltage coefficients which means that the capacitance values decrease even more when used at the rated voltage. x5r and x7r type ceramics are recom- mended for their lower voltage and temperature coef- ficients. another consideration when using ceramics is their high q which, if not properly damped, may result in excessive voltage stress on the power mosfets. alumi- num electrolytics have much higher bulk capacitance, but they have higher esr and lower rms current ratings. a good approach is to use a combination of aluminum electrolytics for bulk capacitance and ceramics for low esr and rms current. if the rms current cannot be handled by the aluminum capacitors alone, when used together, the percentage of rms current that will be supplied by the aluminum capacitor is reduced to approximately: % i rms,alum 1 1 + (8fcr esr ) 2 ? 100% where r esr is the esr of the aluminum capacitor and c is the overall capacitance of the ceramic capacitors. using an aluminum electrolytic with a ceramic also helps damp the high q of the ceramic, minimizing ringing. output capacitor selection the selection of c out is primarily determined by the esr required to minimize voltage ripple. the output ripple (dv out ) is approximately equal to: v out i l esr + 1 8fc out ? ? ? ? ? ? since di l increases with input voltage, the output ripple is highest at maximum input voltage. esr also has a sig - nificant effect on the load transient response. fast load transitions at the output will appear as voltage across the esr of c out until the feedback loop in the ltc3810-5 can change the inductor current to match the new load current value. typically, once the esr requirement is satisfied the capacitance is adequate for filtering and has the required rms current rating. manufacturers such as nichicon, nippon chemi-con and sanyo should be considered for high performance throughhole capacitors. the os-con (organic semicon - ductor dielectric) capacitor available from sanyo has the lowest product of esr and size of any aluminum electroly- tic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recom- mended to reduce the effect of their lead inductance. in surface mount applications, multiple capacitors placed in parallel may be required to meet the esr, rms current handling and load step requirements. dry tantalum, special polymer and aluminum electrolytic capacitors are available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density a pplica t ions i n f or m a t ion
ltc3810-5 20 38105fd than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. several excellent surge-tested choices are the avx, tps and tpsv or the kemet t510 series. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-driven applications providing that consideration is given to ripple current ratings and long term reliability. other capacitor types include panasonic sp and sanyo poscaps. output voltage the ltc3810-5 output voltage is set by a resistor divider according to the following formula: v out = 0.8v 1 + r fb1 r fb2 ? ? ? ? ? ? the external resistor divider is connected to the output as shown in the functional diagram, allowing remote voltage sensing. the resultant feedback signal is compared with the internal precision 800mv voltage reference by the error amplifier. the internal reference has a guaranteed tolerance of less than 1%. tolerance of the feedback resistors will add additional error to the output voltage. 0.1% to 1% resistors are recommended. input voltage undervoltage lockout a resistor divider connected from the input supply to the uvin pin (see functional diagram) is used to program the input supply undervoltage lockout thresholds. when the rising voltage at uvin reaches 0.88v the ltc3810 turns on, and when the falling voltage at uvin drops below 0.8v, the ltc3810 is shut downproviding 10% hysterisis. the input voltage uvlo thresholds are set by the resistor divider according to the following formulas: v in,falling = 0.8v (1 + r uv1 /r uv2 ) and v in,rising = 0.88v (1 + r uv1 /r uv2 ) if input supply undervoltage lockout is not needed, it can be disabled by connecting uvin to intv cc . top mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from drv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications 0.1f to 0.47f , x5r or x7r dielectric capacitor is adequate. the reverse breakdown of the external diode, d b , must be greater than v in(max) . another important consideration for the external diode is the reverse recovery and reverse leak - age, either of which may cause excessive reverse current to flow at full reverse voltage. if the reverse current times reverse voltage exceeds the maximum allowable power dissipation, the diode may be damaged. for best results, use an ultrafast recovery diode such as the mmdl770t1. bottom mosfet driver return supply (bgrtn) the bottom gate driver, bg, switches from drv cc to bgrtn where bgrtn can be a voltage between ground and C5v. why not just keep it simple and always connect bgrtn to ground? in high voltage switching converters, the switch node dv/dt can be many volts/ns, which will pull up on the gate of the bottom mosfet through its miller capacitance. if this miller current, times the internal gate resistance of the mosfet plus the driver resistance, exceeds the threshold of the fet, shoot-through will oc - cur. by using a negative supply on bgrtn, the bg can be pulled below ground when turning the bottom mosfet off. this provides a few extra volts of margin before the gate reaches the turn-on threshold of the mosfet. be aware that the maximum voltage difference between drv cc and bgrtn is 14v. if, for example, v bgrtn = C2v, the maximum voltage on drv cc pin is now 12v instead of 14v. ic/mosfet driver supplies (intv cc and drv cc ) the ltc3810-5 drivers are supplied from the drv cc and boost pins (see figure 2), which have an absolute maximum voltage of 14v. since the main supply voltage, applica t ions in f or m a t ion
ltc3810-5 21 38105fd v in is typically much higher than 14v a separate supply for the ic power (intv cc ) and driver power (drv cc ) must be used. the ltc3810-5 has integrated bias supply con - trol circuitry that allows the ic/driver supply to be easily generated from v in and/or v out with minimal external components. there are four ways to do this as shown in the simplified schematics of figure 3 and explained in the following sections. using the linear regulator for intv cc /drv cc supply i n mode 1, a small external sot23 mosfet, controlled by the ndrv pin, is used to generate a 5.5v start-up supply from v in . the small sot23 package can be used because the nmos is on continuously only during the brief start-up period. as soon as the output voltage reaches 4.7v, the ltc3810-5 turns off the external nmos and the ltc3810-5 regulates the 5.5v supply from the extv cc pin (connected to v out or a v out derived boost network) through an internal low dropout regulator. for this mode to work properly, extv cc must be in the range 4.7v < extv cc < 15v. if v out < 4.7v, a charge pump or extra winding can be used to raise extv cc to the proper voltage, or alter - natively, mode 2 should be used as explained later in this section. if v out is shorted or otherwise goes below the minimum 4.5v threshold, the mosfet connected to v in is turned back on to maintain the 5.5v supply. however if the output cannot be brought up within a timeout period, the drivers are turned off to prevent the sot23 mosfet from overheating. soft-start cycles are then attempted at low duty cycle intervals to try to bring the output back up (see figure 10). this fault timeout operation is enabled by choosing the choosing r ndrv such that the resistor current i ndrv is greater than 270a by using the follow- ing formulas: r ndrv p mosfet(max) / i cc ? v th 270 a where i cc = (f) q g(top) + q g(bottom) ( ) + 3ma and v th is the threshold voltage of the mosfet. the value of r ndrv also affects the v in(min) as follows: v in(min) = v intvcc(min) + (40a) r ndrv +v t (1) where v intvcc(min) is normally 4.5v for driving logic-level mosfets. if minimum v in is not low enough, consider reducing r ndrv and/or using a darlington npn instead of an nmos to reduce v t to ~1.4v. when using r ndrv equal to the computed value, the ltc3810-5 will enable the low duty cycle soft-start re - tries only when the desired maximum power dissipation, p mosfet(max) , in the mosfet is exceeded and leave the drivers on continuously otherwise. the shutoff/restart times are a function of the track/ss capacitor value. the external nmos for the linear regulator should be a standard 3v threshold type (i.e., not a logic-level threshold). the rate of charge of intv cc from 0v to 5.5v is controlled by the ltc3810-5 to be approximately 75s regardless of the size of the capacitor connected to the intv cc pin. the charging current for this capacitor is approximately: i c = 5.5v 75 s ? ? ? ? ? ? c intvcc figure 10. fault timeout operation ss/track v out tg/bg fault timeout enabled extv cc uv threshold driver off threshold driver power from v in short-circuit event start-up into short-circuit start-up driver power from v out driver power from v in i ss/track = 1.4a (source) i ss/track = 0.1a (sink) 38105 f10 a pplica t ions i n f or m a t ion
ltc3810-5 22 38105fd the safe operating area (soa) for the external nmos should be chosen so that capacitor charging does not damage the nmos. excessive values of capacitor are unnecessary and should be avoided. typically values in the 1f to 10f work well. one more design requirement for this mode is the minimum soft-start capacitor value. the fault timeout is enabled when ss/track voltage is greater than 4v. this gives the power supply time to bring the output up before it starts the timeout sequence. to prevent timeout sequence from starting prematurely during start-up, a minimum c ss value is necessary to ensure that v ss/track < 4v until v extvcc > 4.7v. to ensure this, choose: c ss > c out ? (2.3 ? 10 C6 )/i out(max) mode 2 should be used if v out is outside of the 4.7v < extv cc < 15v operating range and the extra complexity of a charge pump or extra inductor winding is not wanted to boost this voltage above 4.7v. in this mode, extv cc is grounded and the nmos is chosen to handle the worst- case power dissipation: p mosfet = v in(max) ( ) f ( ) q g(top) + q g(bottom) ( ) + 3ma ? ? ? ? to operate properly, the fault timeout operation must be disabled by choosing r ndrv > (v in(max) C 5.5v C v th )/270a if the required r ndrv value results in an unacceptable value for v in(min) (see equation 1), fault timeout operation can also be disabled by connecting a 500k to 1meg resistor from ss/track pin to intv cc . using trickle charge mode trickle charge mode is selected by shorting ndrv and intv cc and connecting extv cc to v out . trickle charge mode has the advantage of not requiring an external mosfet but takes longer to start up due to slow charge up of c intvcc and c drvcc through r pullup (t delay = 0.77 ? r pullup ? c drvcc ) and usually requires larger intv cc / drv cc capacitor values to hold up the supply voltage dur - ing start-up. once the intv cc /drv cc voltage reaches the trickle charge uv threshold of 9v, the drivers will turn on and start discharging c intvcc /c drvcc at a rate determined by the driver current i g . in order to ensure proper start- up, c intvcc /c drvcc must be chosen large enough so that the extv cc voltage reaches the switchover threshold of 4.7v before c intvcc /c drvcc discharges below the falling uv threshold of 4v. this is ensured if: c intvcc + c drvcc > i g ? largerof c out i max or 5.5 ? 10 5 ? c ss v out(reg) ? ? ? ? ? ? where i g is the gate drive current = (f)(q g(top) + q g(bottom) ) and i max is the maximum inductor current selected by v rng . for r pullup , the value should fall in the following range to ensure proper start-up: min r pullup > (v in(max) C 14v)/i ccsr max r pullup < (v in(min) C 9v)/i q,shutdown using an external supply connected to the intv cc / drv cc pins if an external supply is available between 4.5v and 14v, the supply can be connected directly to the intv cc /drv cc pins. in this mode, intv cc , extv cc and ndrv must be shorted together. intv cc /drv cc supply and the extv cc connection the ltc3810-5 contains an internal low dropout regulator to produce the 5.5v intv cc /drv cc supply from the extv cc pin voltage. this regulator turns on when the extv cc pin is above 4.7v and remains on until extv cc drops below 4.45v. this allows the ic/mosfet power to be derived from the output or an output derived boost network during normal operation and from the external nmos from v in during start-up or short-circuit. using the extv cc pin in this way results in significant efficiency gains compared to what would be possible when deriving this power continuously from the typically much higher v in voltage. the extv cc connection also allows the power supply to be configured in trickle charge mode in which it starts up with a high valued bleed resistor connected from v in to intv cc to charge up the intv cc capacitor. as soon as the output rises above 4.7v the internal extv cc regulator applica t ions in f or m a t ion
ltc3810-5 23 38105fd takes over before the intv cc capacitor discharges below the uv threshold. when the extv cc regulator is active, the extv cc pin can supply up to 50ma rms. do not ap- ply more than 15v to the extv cc pin. the following list summarizes the possible connections for extv cc : 1. extv cc grounded. this connection will require intv cc to be powered continuously from an external nmos from v in resulting in an efficiency penalty as high as 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for 4.7v < v out < 15v and provides the highest efficiency. the power supply will start up using an external nmos or a bleed resistor until the output supply is available. 3. extv cc connected to an output-derived boost network. if v out < 4.7v. the low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7v. 4. extv cc connected to intv cc . this is the required con - nection for extv cc if intv cc is connected to an external supply where the external supply is 4.5v < v ext < 15v. applications using large mosfets with a high input voltage and high frequency of operation may result in a large extv cc pin current. due to the ltc3810-5 thermally enhanced package, maximum junction temperature will rarely be exceeded, however, it is good design practice to verify that the maximum junction temperature rating and rms current rating are within the maximum limits. typically, most of the extv cc current consists of the mosfet gates current. in continuous mode operation, this extv cc current is: i extvcc = f q g(top) + q g(bottom) ( ) + 3ma < 50ma the junction temperature can be estimated from the equations given in note 2 of the electrical characteristics as follows: t j = t a + i extvcc ? (v extvcc C v intvcc )(34c/w) the calculated t j should be <125c for e- and i-grade or < 150c for h-grade. if absolute maximum ratings are exceeded, consider using an external supply connected directly to the intv cc pin. feedback loop/compensation feedback loop types in a typical ltc3810-5 circuit, the feedback loop con - sists of the modulator, the output filter and load, and the feedback amplifier with its compensation network. all of these components affect loop behavior and must be ac- counted for in the loop compensation. the modulator and output filter consists of the internal current comparator, the output mosfet drivers and the external mosfets, inductor and output capacitor. current mode control eliminates the effect of the inductor by moving it to the inner loop, reducing it to a first order system. from a feedback loop point of view, it looks like a linear voltage controlled current source from i th to v out and has a gain equal to (i max r out )/1.2v. it has fairly benign ac behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. the external output capacitor and load cause a first order roll off at the output at the r out c out pole frequency, with the attendant 90 phase shift. this roll off is what filters the pwm waveform, resulting in the desired dc output voltage. the output capacitor also contributes a zero at the c out r esr frequency which adds back the 90 phase and cancels the first order roll off. so far, the ac response of the loop is pretty well out of the users control. the modulator is a fundamental piece of the ltc3810-5 design and the external output capacitor is usually chosen based on the regulation and load current requirements without considering the ac loop response. the feedback amplifier, on the other hand, gives us a handle with which to adjust the ac response. the goal is to have 180 phase shift at dc (so the loop regulates), and something less than 360 phase shift (preferably about 300) at the point that the loop gain falls to 0db, i.e., the crossover frequency, with as much gain as possible at frequencies below the crossover frequency. since the modulator/output filter is a first order system with maxi- mum of 90 phase shift (at frequencies below f sw /4) and the feedback amplifier adds another 90 of phase shift, some phase boost is required at the crossover frequency to achieve good phase margin. if the esr zero is below the crossover frequency, this zero may provide enough phase boost to achieve the desired phase margin and the only a pplica t ions i n f or m a t ion
ltc3810-5 24 38105fd figure 11. type 2 schematic and transfer function requirement of the compensation will be to guarantee that the gain is below zero at frequencies above f sw /4. if the esr zero is above the crossover frequency, the feedback amplifier will probably be required to provide phase boost. for most ltc3810-5 applications, type 2 compensation will provide enough phase boost; however some applications where high bandwidth is required with low esr ceramics and lots of bulk capacitance, type 3 compensation may be necessary to provide additional phase boost. the two types of compensation networks, type 2 and type 3 are shown in figures 11 and 12. when compo - nent values are chosen properly, these networks provide a phase bump at the crossover frequency. type 2 uses a single pole-zero pair to provide up to about 60 of phase boost while type 3 uses two poles and two zeros to provide up to 150 of phase boost. figure 12. type 3 schematic and transfer function feedback component selection selecting the r and c values for a typical type 2 or type 3 loop is a nontrivial task. the applications shown in this data sheet show typical values, optimized for the power components shown. they should give acceptable perfor - mance with similar power components, but can be way off if even one major power component is changed significantly. applications that require optimized transient response will require recalculation of the compensation values specifically for the circuit in question. the underlying mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover frequency. modulator gain and phase can be obtained in one of three ways: measured directly from a breadboard, or if the appropriate parasitic values are known, simulated or generated from the modulator transfer function. mea- surement will give more accurate results, but simulation or transfer function can often get close enough to give a working system. to measure the modulator gain and phase directly, wire up a breadboard with an ltc3810-5 and the actual mosfets, inductor and input and output capacitors that the final design will use. this breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the ltc3810-5, no long wires connecting components, appropriately sized ground returns, etc. wire the feedback amplifier with a 0.1f feedback capacitor from i th to fb and a 10k to 100k resistor from v out to fb. choose the bias resistor (r fb2 ) as required to set the desired output voltage. disconnect r fb2 from ground and connect it to a signal generator or to the source output of a network analyzer to inject a test signal into the loop. measure the gain and phase from the i th pin to the output node at the positive terminal of the output capacitor. make sure the analyzers input is ac coupled so that the dc voltages present at both the i th and v out nodes dont corrupt the measurements or damage the analyzer. if breadboard measurement is not practical, a spice simulation can be used to generate approximate gain/ phase curves. plug the expected capacitor, inductor and mosfet values into the following spice deck and gener - ate an ac plot of v out /v ith with gain in db and phase in applica t ions in f or m a t ion gain (db) 38105 f11 0 phase ?6db/oct ?6db/oct gain phase (deg) freq ?90 ?180 ?270 ?360 r fb2 v ref r fb1 r2 fb c2 in out + ? c1 gain (db) 38105 f12 0 phase ?6db/oct +6db/oct ?6db/oct gain phase (deg) freq ?90 ?180 ?270 ?360 v ref r2 fb c2 in out + ? c1 c3 r3 r fb2 r fb1
ltc3810-5 25 38105fd degrees. refer to your spice manual for details of how to generate this plot. *3810-5 modulator gain/phase *2006 linear technology *this file simulates a simplified model of *the ltc3810-5 for generating a v(out)/ v(ith) *bode plot .param rdson=.0135 ;mosfet rdson .param vrng=2 ;use 1.4 for intvcc and 0.7 for ground .param vsnsmax={0.173*vrng-0.026} .param imax={vsnsmax/rdson} .param dl=4 ;inductor ripple current *inductor current gl out 0 value={(v(ith)-1.2)*imax/1.2+dl/2} *output cap cout out out2 270u ;capacitor value resr out2 0 0.018 ;capacitor esr *load rout out 0 2 ; load resistor vstim ith 0 0 ac 1 ;ac stimulus .ac dec 100 100 10meg .probe .end mathematical software such as mathcad or matlab can also be used to generate plots using the following transfer function of the modulator: h(s) = v sense(max) 1.2 ? r ds(on) ? ? ? ? ? ? ? 1+ s ? r esr ? c out 1+ s ? r l ? c out ? ? ? ? ? ? ? r l s = j2 f (2) with the gain/phase plot in hand, a loop crossover fre- quency can be chosen. usually the cur ves look something like figure 13. choose the crossover frequency about 25% of the switching frequency for maximum bandwidth. al- though it may be tempting to go beyond f sw /4, remember that significant phase shift occurs at half the switching frequency that isnt modeled in the above h(s) equation and pspice code. note the gain (gain, in db) and phase (phase, in degrees) at this point. the desired feedback amplifier gain will be Cgain to make the loop gain at 0db at this frequency. now calculate the needed phase boost, assuming 60 as a target phase margin: boost = C (phase + 30) if the required boost is less than 60, a type 2 loop can be used successfully , saving two external components. boost values greater than 60 usually require type 3 loops for satisfactory performance. finally, choose a convenient resistor value for r fb1 (10k is usually a good value). now calculate the remaining values: (k is a constant used in the calculations) f = chosen crossover frequency g = 10 (gain/20) (this converts gain in db to g in absolute gain) type 2 loop: k = tan boost 2 + 45 ? ? ? ? ? ? c2 = 1 2 ? f ? g ? k ? r fb1 c1 = c2 k 2 ? 1 ( ) r2 = k 2 ? f ? c1 r fb2 = v ref (r fb1 ) v out ? v ref a pplica t ions i n f or m a t ion figure 13. transfer function of buck modulator frequency (hz) gain (db) phase (deg) 38105 f13 0 0 ?90 ?180 gain phase
ltc3810-5 26 38105fd for spice, replace vstim line in the previous pspice code with following code and generate a gain/phase plot of v(out)/v(outin): rfb1 outin vfb 52.5k rfb2 vfb 0 10k eithx ithx 0 laplace {0.8-v(vfb)} = {1/(1+s/1000)} eith ith 0 value={limit(1e6*v(ithx),0,2.4)} cc1 ith vfb 4p cc2 ith x1 8p rc x1 vfb 210k rf outin x2 11k ;delete this line for type 2 cf x2 vfb 120p ;delete this line for type 2 vstim out outin dc=0 ac=1m pulse skip mode operation and mode/sync pin the mode/sync pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 0.8v threshold enables pulse skip mode operation where the bottom mosfet turns off when inductor current reverses. the load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in v in . tying the mode/sync pin below the 0.8v threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. to prevent forcing current back into the main power supply, potentially boosting the input supply to a dangerous voltage level, forced continuous mode of operation is disabled when the track/ss voltage is below the reference voltage during soft-start or tracking. during these two periods, the pgood signal is forced low. table 1 mode/sync pin condition dc voltage: 0v to 0.75v forced continuous current reversal enabled dc voltage: 0.85v pulse skip mode operation no current reversal feedback resistors regulating a secondary winding ext. clock 0v to 2v forced continuous current reversal enabled type 3 loop: k = tan 2 boost 4 + 45 ? ? ? ? ? ? c2 = 1 2 ? f ? g ? r fb1 c1 = c2 k ? 1 ( ) r2 = k 2 ? f ? c1 r3 = r fb1 k ? 1 c3 = 1 2 f k ? r3 r fb2 = v ref (r fb1 ) v out ? v ref spice or mathematical software can be used to generate the gain/phase plots for the compensated power supply to do a sanity check on the component values before trying them out on the actual hardware. for software, use the following transfer function: t(s) = a(s)h(s) where h(s) was given in equation 2 and a(s) depends on compensation circuit used: t ype 2: a (s) = 1+ s ? r2 ? c1 s ? r fb1 ? c1 + c2 ( ) ? 1+ s ? r2 ? c1 ? c2 c1 + c2 ? ? ? ? ? ? type 3: a (s) = 1 s ? r fb1 ? c1 + c2 ( ) ? 1+ s ? r fb1 + r3 ( ) ? c3 ( ) ? 1+ s ? r2 ? c1 ( ) 1+ s ? r3 ? c3 ( ) ? 1+ s ? r2 ? c1 ? c2 c1 + c2 ? ? ? ? ? ? applica t ions in f or m a t ion
ltc3810-5 27 38105fd figure 14. secondary output loop in addition to providing a logic input to force continu - ous operation, the mode/sync pin provides a mean to maintain a flyback winding output when the primary is operating in pulse skip mode. the secondary output v out2 is normally set as shown in figure 14 by the turns ratio n of the transformer. however, if the controller goes into pulse skip mode and halts switching due to a light primary load current, then v out2 will droop. an external resistor divider from v out2 to the mode/sync pin sets a minimum voltage v out2(min) below which continuous operation is forced until v out2 has risen above its minimum. v out2(min) = 0.8v 1 + r4 r3 ? ? ? ? ? ? fault conditions: current limit and foldback the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc3810-5, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i limit = v sns(max) r ds(on) t + 1 2 ? i l the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambient temperature, conditions that cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed mosfet junction temperature and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on-resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same percentage below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. to further limit current in the event of a short-circuit to ground, the ltc3810-5 includes foldback current limiting. if the output falls by more than 50%, then the maximum sense voltage is progressively lowered to about one-tenth of its full value. be aware also that when the fault timeout is enabled for the external nmos regulator, an over current limit may cause the output to fall below the minimum 4.5v uv threshold. this condition will cause a linear regulator time - out/restart sequence as described in the linear regulator timeout section if this condition persists. soft-start and tracking the ltc3810-5 has the ability to either soft-start by itself with a capacitor or track the output of another supply. when the device is configured to soft-start by itself, a capacitor should be connected to the track/ss pin. the ltc3810-5 is put in a low quiescent current shutdown state (i q ~240a) if the shdn pin voltage is below 1.5v. the track/ss pin is actively pulled to ground in this shutdown state. once the shdn pin voltage is above 1.5v, the ltc3810-5 is powered up. a soft-start current of 1.4a then starts to charge the soft-start capacitor c ss . note that soft-start is achieved not by limiting the maxi- mum output current of the controller but by controlling the ramp rate of the output voltage. current foldback is disabled during this soft-start phase. during the soft-start phase, the ltc3810 - 5 is ramping the reference voltage until it reaches 0.8v . the force continuous mode is also a pplica t ions i n f or m a t ion v in ltc3810-5 sgnd fcb tg sw r3 r4 38105 f14 t1 1:n bg pgnd + c out2 1f v out1 v out2 v in + c in 1n4148 ? ? + c out
ltc3810-5 28 38105fd disabled and pgood signal is forced low during this phase. the total soft-start time can be calculated as: t softstart = 0.8 ? c ss /1.4a when the device is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the track/ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply output voltage. output voltage tracking the ltc3810-5 allows the user to program how its out - put ramps up by means of the track/ss pin. through this pin, the output can be set up to either coincidentally or ratiometrically track with another supplys output, as shown in figure 15. in the following discussions, v out1 refers to the master ltc3810-5s output and v out2 refers to the slave ltc3810-5s output. to implement the coincident tracking in figure 15a, con - nect an additional resistive divider to v out1 and connect its midpoint to the track/ss pin of the slave ic. the ratio of this divider should be selected the same as that of the slave ics feedback divider shown in figure 16. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking, the ratio of the divider should be exactly the same as the master ics feedback divider. note that the internal soft-start current will introduce a small error on the tracking voltage depending on the absolute values of the tracking resistive divider. by selecting different resistors, the ltc3810-5 can achieve different modes of tracking including the two in figure 15. so which mode should be programmed? while either mode in figure 15 satisfies most practical applications, there do exist some tradeoffs. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. this can be better understood with the figure 15. two different modes of output voltage tracking figure 16. setup for coincident and ratiometric tracking applica t ions in f or m a t ion time (15a) coincident tracking v out1 v out2 output voltage time 38105 f15 (15b) ratiometric tracking v out1 v out2 output voltage r3 r1 r4 r2 r3 v out2 r4 (16a) coincident tracking setup to v fb1 pin to track/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 38105 f16 (16b) ratiometric tracking setup to v fb1 pin to track/ss2 pin to v fb2 pin v out1
ltc3810-5 29 38105fd the internal oscillator locks to the external clock after the second clock transition is received. when external synchronization is detected, ltc3810-5 will operate in forced continuous mode. if an external clock transition is not detected for three successive periods, the internal oscillator will revert to the frequency programmed by the r on resistor. during the start-up phase, phase-locked loop function is disabled. when ltc3810-5 is not in synchronization mode, pll/lpf pin voltage is set to around 1.215v. frequency synchronization is accomplished by changing the internal on-time current according to the voltage on the pll/lpf pin. the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the ex - ternal and internal pulses. this type of phase detector will not lock up on input frequencies close to the harmonics of the v co center frequency. the pll hold-in range, df h , is equal to the capture range, df c: df h = df c = 0.3 f o the output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the pll /lpf pin. a simplified block diagram is shown in figure 18. figure 17. equivalent input circuit of error amplifier a pplica t ions i n f or m a t ion ? + i i d1 track/ss2 0.8v v fb2 d2 d3 38105 f17 ea2 help of figure 17. at the input stage of the slave ics error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same amplitude. in the coincident mode, the track/ss voltage is substantially higher than 0.8v at steady state and effectively turns off d1. d2 and d3 will therefore conduct the same current and offer tight matching between v fb2 and the internal precision 0.8v reference. in the ratiometric mode, however, track/ss equals 0.8v at steady state. d1 will divert part of the bias current to make v fb2 slightly lower than 0.8v. although this error is minimized by the exponential i-v characteristic of the diode, it does impose a finite amount of output voltage deviation. furthermore, when the master ics output experiences dynamic excursion (under load transient, for example), the slave ic output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. phase-locked loop and frequency synchronization the ltc3810-5 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this allows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 30% around the center frequency f o . the center frequency is the operating frequency discussed in the operating frequency section. the ltc3810-5 incorporates a pulse detection circuit that will detect a clock on the mode/sync pin. in turn, it will turn on the phase-locked loop function. the pulse width of the clock has to be greater than 400ns and the amplitude of the clock should be greater than 2v. figure 18. phase-locked loop block diagram digital phase/ frequency detector mode/sync pll/lpf 2.4v c lp 38105 f18 r lp vco
ltc3810-5 30 38105fd if the external frequency (f mode ) is greater than the oscillator frequency f o , current is sourced continuously, pulling up the pll /lpf pin. when the external frequency is less than f o , current is sunk continuously, pulling down the pll /lpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus the voltage on the pll/lpf pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor c lp holds the voltage. the ltc3810-5 mode/ sync pin must be driven from a low impedance source such as a logic gate located close to the pin. the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 0.01f to 0.1f. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3810-5 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the efficiency to drop at high output currents. in continuous mode the average output current flows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 and r l = 0.005, the loss will range from 15mw to 1.5w as the output current varies from 1a to 10a. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is signifi - cant at input voltages above 20v and can be estimated from the second term of the p main equation found in the power mosfet selection section. when transition losses are significant, efficiency can be improved by lowering the frequency and/or using a top mosfet(s) with lower c rss at the expense of higher r ds(on) . 3. intv cc /drv cc current. this is the sum of the mosfet driver and control currents. control current is typically about 3ma and driver current can be calculated by: i gate = f(q g(top) + q g(bot) ), where q g(top) and q g(bot) are the gate charges of the top and bottom mosfets. this loss is proportional to the supply voltage that intv cc /drv cc is derived from, i.e., v in for the external nmos linear regulator, v out for the internal extv cc regulator, or v ext when an external supply is connected to intv cc /drv cc . 4. c in loss. the input capacitor has the difficult job of fil- tering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. other losses, including c out esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve efficiency, the input cur - rent is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. if there is no change in input current, then there is no change in efficiency. checking transient response the regulator loop response can be checked by look- ing at the load transient response. switching regulators take several cycles to respond to a step in load current. applica t ions in f or m a t ion
ltc3810-5 31 38105fd when load step occurs, v out immediately shifts by an amount equal to di load (esr), where esr is the effective series resistance of c out . di load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. design example as a design example, take a supply with the following specifications: v in = 12v to 60v, v out = 5v 5%, i out(max) = 6a, f = 250khz. first, calculate the timing resistor: r on = 5v 2.4v ? 250khz ? 76pf = 110k and choose the inductor for about 40% ripple current at the maximum v in : l = 5v 250khz ? 0.4 ? 6a 1? 5v 60v ? ? ? ? ? ? = 7.6 h with a 7.7h inductor, ripple current will vary from 1.5a to 2.4a (25% to 40%) over the input supply range. next, choose the bottom mosfet switch. since the drain of the mosfet will see the full supply voltage 60v (max) plus any ringing, choose an 60v mosfet. the si7850dp has: bv dss = 60v r ds(on) = 31m (max)/25m (nom), = 0.007/c, c miller = (8.3nc C 2.8nc)/30v = 183pf, v gs(miller) = 3.8v, ja = 22c/w. this yields a nominal sense voltage of: v sns(nom) tt = 195mv to guarantee proper current limit at worst-case conditions, increase nominal v sns by at least 50% to 320mv (by tying v rng to 2v). to check if the current limit is acceptable at v sns = 320mv, assume a junction temperature of about 55c above a 70c ambient ( 125c = 1.7): i limit 320mv 1.7 ? 0.031 + 1 2 ? 2.4a = 7.3a and double-check the assumed t j in the mosfet: p bot = 60v ? 5v 60v ? 7.3a 2 ? 1.7 ? 0.031 = 2.6w t j 8t8 verify that the si7850dp is also a good choice for the top mosfet by checking its power dissipation at current limit and maximum input voltage, assuming a junction temperature of 30c above a 70c ambient ( 100c = 1.5): p main = 5v 60v ? 7.3a 2 1.5 ? 0.031 ( ) + 60v 2 ? 7.3a 2 ? 2 ? 183pf ? 1 5v ? 3.8v + 1 3.8v ? ? ? ? ? ? ? 250khz = 0.206w + 1.32w = 1.53w t j 8t8 the junction temperature will be significantly less at nomi- nal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in this circuit. since v out > 4.7v, the intv cc voltage can be generated from v out with the internal ldo by connecting v out to the extv cc pin. a small sot23 mosfet such as the zxmn10a07f can be used for the pass device if fault timeout is enabled. choose r ndrv to guarantee that fault timeout is enabled when power dissipation of m3 exceeds 0.4w (max for 70c ambient): i cc l)ttonn r ndrv 0.4w / 0.012a ? 3v 270a = 112k so, choose r ndrv = 100k. a pplica t ions i n f or m a t ion
ltc3810-5 32 38105fd c in is chosen for an rms current rating of about 3a at 85c. the output capacitors are chosen for a low esr of 0.018 to minimize output voltage changes due to inductor ripple current and load steps. the ripple voltage will be only: dv out(ripple) = di l(max) ? esr = 2.4a ? 0.018w = 43mv however, a 0a to 6a load step will cause an output change of up to: dv out(step) = di load ? esr = 6a ? 0.018 = 108mv an optional 10f ceramic output capacitor is included to minimize the effect of esl in the output ripple. the complete circuit is shown in figure 19. pc board layout checklist when laying out a pc board follow one of two suggested approaches. the simple pc board layout requires a dedi- cated ground plane layer. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. ? the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. ? place c in , c out , mosfets, d1 and inductor all in one compact area. it may help to have some components on the bottom side of the board. ? use an immediate via to connect the components to ground plane including sgnd and pgnd of ltc3810-5. use several bigger vias for power components. applica t ions in f or m a t ion figure 19. 12v to 60v input voltage to 5v/6a synchronized at 250khz pgood mode_sync pgood 250khz clock v on v rng i th sgnd u vin shdn v fb sgnd pgnd pgnd ss/track i on pll/lpf c on 100pf c ss 1000pf v in 12v to 60v v out 5v 6a m3 zxmn10a07f c c2 47pf r c 200k r fb2 1.91k r fb1 10k ltc3810-5 extv cc tg sense ? bg bgrtn drv cc intv cc ndrv boost 38105 f19 c b 0.1f 0.01f 10k 78.7k 10k c drvcc 0.1f c vcc 1f r uv2 14.3k r uv1 200k r on 110k r ndrv 100k db bas19 m1 sir880dp m2 sir880dp c5 1f d1 b1100 c out1 270f 6.3v c out2 10f 6.3v l1 10h shdn 31 2 3 4 5 6 7 8 9 33 12 13 27 26 20 19 18 17 16 15 14 c c1 5pf c in1 68f 100v c in2 1f 100v sw sense + 25 24
ltc3810-5 33 38105fd a pplica t ions i n f or m a t ion ? use compact plane for switch node (sw) to improve cooling of the mosfet s and to keep emi down. ? use planes for v in and v out to maintain good voltage filtering and to keep power losses low. ? flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power component. you can connect the copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system). when laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper opera - tion of the controller. ? segregate the signal and power grounds. all small signal components should return to the sgnd pin at one point which is then tied to the pgnd pin close to the source of m2. ? place m2 as close to the controller as possible, keeping the pgnd, bg and sw traces short. ? connect the input capacitor(s) c in close to the pow- er mosfets. this capacitor carries the mosfet ac current. ? keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. ? connect the intv cc decoupling capacitor c vcc closely to the intv cc and sgnd pins. ? connect the top driver boost capacitor c b closely to the boost and sw pins. ? connect the bottom driver decoupling capacitor c drvcc closely to the drv cc and bgrtn pins.
ltc3810-5 34 38105fd typical a pplica t ions pgood mode_sync pgood v on v rng i th sgnd uvin shdn v fb sgnd pgnd pgnd ss/track i on pll/lpf c on 100pf c ss 1000pf v in 7v to 60v v out 5v 5a 12v c c2 47pf r c 100k r fb2 1.91k r fb1 10k ltc3810-5 extv cc tg sense ? bg bgrtn drv cc intv cc ndrv boost 38105 ta03 c b 0.1f c drvcc 0.1f c vcc 1f r uv2 61.9k r uv1 470k r on 110k db bas19 m1 si7850dp m2 si7850dp c5 22f d1 b1100 c out 47f 6.3v 3 l1 4.7h shdn 31 2 3 4 5 6 7 8 9 33 12 13 27 26 20 19 18 17 16 15 14 c c1 5pf c in1 68f 100v c in2 1f 100v sw sense + 25 24 7v to 60v input voltage to 5v/5a with ic power from 12v supply and all ceramic output capacitors
ltc3810-5 35 38105fd 15v to 60v input voltage to 3.3v/5a with fault timeout, pulse skip and v in uv disabled t ypical a pplica t ions pgood mode_sync pgood v on v rng i th sgnd uvin shdn v fb sgnd pgnd pgnd ss/track i on pll/lpf c on 100pf c ss 1000pf v in 15v to 60v v out 3.3v 5a m3 zvn4210g c c2 47pf r c 200k r fb2 3.24k r fb1 10.2k ltc3810-5 extv cc tg sense ? bg bgrtn drv cc intv cc ndrv boost 38105 ta04 c b 0.1f c drvcc 0.1f c vcc 1f r on 71.5k r ndrv 215k db bas19 m1 si7850dp m2 si7850dp c5 1 f d1 b1100 c out1 270f 6.3v c out2 10f 6.3v l1 4.7h shdn 31 2 3 4 5 6 7 8 9 33 12 13 27 26 20 19 18 17 16 15 14 c c1 5pf c in1 68f 100v c in2 1f 100v sw sense + 25 24
ltc3810-5 36 38105fd uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) p ackage descrip t ion 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05
ltc3810-5 37 38105fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number d 12/10 change to operating temperature range updated order information table change made to feedback voltage (v fb ) change to note 2 and note 7 addition of 150c to graphs g14, g17, g18, g19, g20, g23, g24, g25, g28 and g30 formula change: type 2 and type 3 updated related parts table 2 2 3 4 6, 7, 8 26 38 (revision history begins at rev d)
ltc3810-5 38 38105fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com ? linear technology corporation 2007 lt 1210 rev d ? printed in usa part number description comments ltc3891 60v, low i q , synchronous step-down dc/dc controller pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, tssop-20e, 3mm 4mm qfn-20 ltc3890 60v, low i q , dual output 2-phase synchronous step-down dc/dc controller pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, 5mm 5mm qfn-32 ltc3810 100v synchronous step-down dc/dc controller constant on-time valley current mode, 4v v in 60v, 0.8v v out 0.93v in , ssop-28 ltc3812-5 60v synchronous step-down dc/dc controller constant on-time valley current mode, 4v v in 60v, 0.8v v out 0.93v in , tssop-16e ltc3703 100v synchronous step-down dc/dc controller pll fixed frequency 100khz to 600khz, 4v v in 100v, 0.8v v out 0.93v in , ssop-16, ssop-28 lt3845a 60v, low i q , single output synchronous step-down dc/dc controller adjustable fixed frequency 100khz to 500khz, 4v v in 60v, 1.23v v out 36v, tssop-16e ltc3824 60v, low i q , step-down dc/dc controller, 100% duty cycle selectable fixed frequency 200khz to 600khz, 4v v in 60v, 0.8v v out v in , i q = 40a, msop-10e 13v to 60v input voltage to 12v/10a with trickle charger start-up pgood mode_sync pgood v on v rng i th sgnd uvin shdn v fb sgnd pgnd pgnd ss/track i on pll/lpf c on 100pf c ss 1000pf v in 13v to 60v v out 12v 10a c c2 47pf r c 200k r fb2 1k r fb1 14k ltc3810-5 extv cc tg sw sense ? bg bgrtn sense + drv cc intv cc ndrv boost 38105 ta05 c b 0.1f c drvcc 0.1f c vcc 1f r uv2 13.3k r uv1 200k r on 263k r ndrv 100k db bas19 m1 si7850dp m2 si7850dp 2 c5 22f d1 b1100 c out1 270f 16v c out2 10f 16v l1 10h shdn 31 2 3 4 5 6 7 8 9 33 12 13 27 26 25 24 20 19 18 17 16 15 14 c c1 5pf c in1 68f 100v c in2 1f 100v r ela t e d p ar t s typical a pplica t ion

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